Despite shrinking IC feature sizes and a reduction in power supply voltages, power consumption of circuits, especially those circuits fabricated using deep submicron technologies, often causes large switching currents to flow in a power distribution network in an IC which can degrade performance and reliability of the IC. A robust power distribution network, which may include power pads, power rings, coupling caps, bond pads, and wire bonds, is therefore essential to ensure reliable operation of circuits in the IC, ideally without sacrificing performance of the IC. This poses a serious problem for the design of the power distribution network.
On-chip power demand is met through external power sources (e.g., power and ground). These external power sources are typically connected to internal power rings, also referred to as buses, which run along a periphery of the IC to deliver the desired power at a specified voltage. Power pad structures, also located around the periphery of the IC, serve to connect the external power supplies to the on-chip power rings as well as to connect the external power supplies to functional circuitry within a core of the IC. Since power pads, as well as input/output (IO) signal pads, serve as interface points between the external world and vulnerable on-chip circuitry, power pads typically employ electrocstatic discharge (ESD) structures. These ESD structures protect the on-chip circuitry from the damaging external voltage surges often attributable to an ESD event. The power pad structure often further includes at least a portion of the power rings, pad pin, core pin, and connections in a given frame. The on-chip functionality will determine the number of power supplies required by the IC. For each power bus of a given type required, there will be a unique set of power rings, as well as a unique set of power pad structures, associated therewith.
One problem in designing a power distribution network in an IC is that there are many unknowns until the end stages of the design cycle. For example, the overall resistance of a given connection will depend upon the layout of that connection in the IC (e.g., the length and width of the connection, how many bends in the connection, whether or not vias are used to connect between two different metal layers, etc.). Nevertheless, it is often necessary to make decisions regarding the structure, size and layout of the power distribution network relatively early in the design cycle, when a large part of the chip design has not even begun. Unfortunately, most commercial verification tools focus on post-layout verification of the power distribution network, after the entire chip design is substantially complete and detailed information about parasitics associated with the power and ground lines and the respective currents drawn by the transistors are known. Power distribution network problems revealed at this stage are usually very difficult and/or costly to fix, so the preferred methodologies help to design an initial power grid and refine it progressively at various stages of the design. Unfortunately, current methodologies tend to be manual and thus time-consuming and error-prone.
While it is known to use automated place and route programs for laying out certain functional circuit blocks and components in the IC, laying out of power pad structures, including placement of ESD and routing of various components of power pads, are typically performed manually due, at least in part, to certain unique characteristics of the structures themselves. Moreover, in performing automated design rule checking (DRC) to verify that an IC layout satisfies prescribed constraints of a given fabrication process, ESD structures are typically removed from consideration since they often generate erroneous DRC errors. These DRC errors must be resolved manually in the ESD structures. Consequently, the placement and routing process, when ESD structures are involved, becomes significantly more tedious, time consuming and prone to errors and is therefore undesirable.
Accordingly, there exists a need for techniques for more optimally placing and routing ESD structures in an IC, as well as establishing the best possible connections among power rings, ESD structures, pad pins, and core pins, which do not suffer from one or more of the above-noted problems associated with conventional design methodologies.